The present invention pertains to cyclic redundancy check (CRC) circuitry and more particularly to circuitry for the generation of CRC information over a number of parallel bits of data.
Modern day technology permits the transfer of large amounts of data between computer or communication systems. During transmission these bits may become altered, thereby creating an error. In order for one computer system to detect when data sent by another computer system has an error, certain status information is often transmitted along with the data. This status information may include parity (even or odd), longitudinal redundancy check character, or cyclic redundancy check character. These are the most commonly used forms for checking the integrity of transmitted data.
For CRC generation, data bits are typically serially input into a CRC generation circuit in order to produce the appropriate CRC character or code for transmission along with the data. The serial processing for the generation of the CRC character is relatively slow when compared with the parallel processing performed by most computers. This parallel processing takes the form of 8-bit, 16-bit, etc. bits of parallel information. It is therefore desirable to speed up the CRC generation process.
One such attempt at more rapid generation of a CRC character is shown in U.S. Pat. No. 4,593,393, issued on June 3, 1986, to B. Mead et al. entitled "Quasi Parallel Cyclic Redundancy Checker" and assigned to the same assignee as the present invention. This patent teaches performing some of the tasks in parallel. However, the CRC information is still generated 1 bit at a time.
U.S. Pat. No. 4,454,600, issued on June 12, 1984, to B. Legresley and U.S. Pat. No. 4,498,174, issued on Feb. 5, 1985, to B. Legresley show quasi parallel CRC character generation. These U.S. Patents present complicated solutions to the CRC generation problem. Further, they are not truly parallel circuits since input selectors 21, 22, 23 and 24 select either one of the input bits for CRC calculation purposes. Therefore, these circuits are somewhat parallel, but extremely costly and complex in design having random access memories comparators and multiple-bit storage devices, along with address generation and selection generation circuitry.
Accordingly, it is an object of the present invention to provide a parallel CRC generation circuit with a minimum of hardware for reducing the number of clock cycles for CRC generation.